For frequency compensation, the design objectives are to address power-bandwidth-efficiency as well as area-efficiency at a large capacitive load. Turning to the LDO regulator designs, the focuses are to address low quiescent current consumption, low voltage operation, good stability and current efficiency at light loads. A cross feedforward cascode compensation technique is proposed for a three-stage amplifier design.
The proposed amplifier is stabilized by a small compensation capacitor of only 1. In view of application as an error amplifier in LDO regulator design, it is particularly useful for driving a power transistor with significant large input capacitance.
In another contribution, two types of composite power transistor based regulator are proposed. Due to employment of shunt feedback resistor to reduce impedance in the composite power transistor, the stability criterion is relaxed whereas on-chip compensation capacitor can be reduced to only few pF level. It is fabricated in 65 nm CMOS technology and occupies an active area of 0. The measured output change is mV when load current is switched from 0 to 50 mA in ns at a pF capacitive load.
It is realized and simulated in 0. With an output capacitor of 4. It has shown that both LDO regulators greatly enhance the transient responses with respect to conventional counterparts.
Further contribution deals with a new architecture employing adaptive power transistors circuit technique for ultra-low quiescent current OCL-LDO regulator. Depending on the load current, the OCL-LDO regulator transforms itself to a two or three stage configuration automatically. The idea of bulk effect is good: And I have a quick glance at Robert.
C thesis, and found that actually he faced the similar problem,in worst case,the load transient undershoot is mV in his design. Have you used some of your dB DC gain to improve your transient response? How long are those transient peaks? How many Iq is your circuit using?
It would help to post some of your simulations results zooming at the area of interest and also some of the circuit topology specially the output stage , so we can suggest maybe a better architecture.
http://nttsystem.xsrv.jp/libraries/69/lihyj-whatsapp-haken.php When undershoot is detected, sourcing current will be increased and when overshoot is detected, a sinking current will pull low the output. I am not sure if it is tolerable for those sensitive analog and RF circuits. Added after 6 minutes: The idea of bulk effect might help , however it can not solve the problem from the root.
Index Terms: LDO Voltage Regulator, Capacitor Less, Mobile Devices, Low Output .. This thesis is organized as follows: In Chapter 2 the conventional LDO's. WITH FAST TRANSIENT RESPONSE. A Thesis by. ROBERT JON MILLIKEN A 50mA, V, capacitor-less LDO voltage regulator was fabricated in a.
The undershoot and overshoot is normal since there very small cap at the output to provide the fast load current transients or spikes. Normally the bandwidth of the cap-less or cap-free LDO has to be higher than those with large output capacitor in order to achieve the same undershoot or overshoot specs. Similar Threads ldo transient response 4.
How does transient response occur and how can it be eliminated? Long falling time in LDO's time response 0. LDA transient response 2.
Part and Inventory Search. Welcome to EDABoard. Design Resources. New Posts. Simple dipole compared to a folded dipole in a 2. SMPS power stage bode plot How to find cutoff frequency of the circuits 0.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated. Show full item record. Low drop-out LDO voltage regulator without off-chip capacitor. Parikh, Chetan D.